H σφαγή του dac...
- Thread starter supersonic
- Start date
JohnJohn
AVClub Addicted Member
- 25 June 2006
- 2,480
JohnJohn
AVClub Addicted Member
- 25 June 2006
- 2,480
JohnJohn
AVClub Addicted Member
- 25 June 2006
- 2,480
Στο pin8 του receiver υπάρχει ένα φιλτρο για το οποιο αντιγράφω απο το datasheet:
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure 23 is a simplified diagram of the PLL. When the PLL is locked to an bi-phase encoded input stream, it is updated at each preamble in the bi-phase encoded stream. This occurs at twice the sampling frequency, FS. There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is important.
For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown in Figure 25. In addition, the PLL has been designed to only use the preambles (PDUR=0) of the bi-phase encoded stream to provide lock update information to the PLL. This results in the PLL being immune to data dependent jitter affects because the preambles do not vary with the data.
The PLL behavior is affected by the external filter component values. Figures 5 and 6 shows the recommended configuration of the two capacitors and one resistor that comprise the PLL filter. In Table 6, the component values shown have a high corner frequency jitter attenuation curve, take a short time to lock, and offer good output jitter performance. Lock times are worst case for an Fsi transition of 192 kHz.
The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable inductance to the circuit. Surface mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted close to the FILT pin to minimize trace inductance. For CRIP, a C0G or NPO dielectric is recommended, and for CFLT, an X7R dielectric is preferred. Avoid capacitors with large temperature co-coefficient, or capacitors with high dielectric constants, that are sensitive to shock and vibration. These include the Z5U and Y5V dielectrics
Table 6. External PLL Component Values
Range (kHz) 32 - 192
RFLT 3 kΩ
CFLT 22 nF
CRIP 1 nF
Settling Time 4 ms
αρα μηπως πρεπει να αλλάξουμε το φιλτρο όπως προτείνουν στο art of sound?
R2 becomes 3k, C22 becomes 22nF, and C23 becomes (COG/NPO) 1 nF
(παλιες τιμες 1Κ, 220nF, 10nF)
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure 23 is a simplified diagram of the PLL. When the PLL is locked to an bi-phase encoded input stream, it is updated at each preamble in the bi-phase encoded stream. This occurs at twice the sampling frequency, FS. There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is important.
For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown in Figure 25. In addition, the PLL has been designed to only use the preambles (PDUR=0) of the bi-phase encoded stream to provide lock update information to the PLL. This results in the PLL being immune to data dependent jitter affects because the preambles do not vary with the data.
The PLL behavior is affected by the external filter component values. Figures 5 and 6 shows the recommended configuration of the two capacitors and one resistor that comprise the PLL filter. In Table 6, the component values shown have a high corner frequency jitter attenuation curve, take a short time to lock, and offer good output jitter performance. Lock times are worst case for an Fsi transition of 192 kHz.
The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable inductance to the circuit. Surface mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted close to the FILT pin to minimize trace inductance. For CRIP, a C0G or NPO dielectric is recommended, and for CFLT, an X7R dielectric is preferred. Avoid capacitors with large temperature co-coefficient, or capacitors with high dielectric constants, that are sensitive to shock and vibration. These include the Z5U and Y5V dielectrics
Table 6. External PLL Component Values
Range (kHz) 32 - 192
RFLT 3 kΩ
CFLT 22 nF
CRIP 1 nF
Settling Time 4 ms
αρα μηπως πρεπει να αλλάξουμε το φιλτρο όπως προτείνουν στο art of sound?
R2 becomes 3k, C22 becomes 22nF, and C23 becomes (COG/NPO) 1 nF
(παλιες τιμες 1Κ, 220nF, 10nF)
- 17 June 2006
- 49,660
JohnJohn
AVClub Addicted Member
- 25 June 2006
- 2,480
- 17 June 2006
- 49,660
Buffer θελω χωρις gain
Ο τελεστικος δινει περιπου 2.4v dc
και κατευθειαν απο το dac περιπου 1.4v dc
Εγω δεν αντεξα να περιμενω και εκανα τις αλλαγες
Η διαφορα προς το καλυτερο ειναι ακουστη αλλα πολυ μικρη
Το ιδιο ειναι με αλλο μετασχηματιστη
Εκανα και εγω ενα τσεκ και απο 3 πωλητες του ebay
τωρα πια μονο ο παραπανω το εχει:nounder::bang::violent-smiley-008::devil-smiley-029::huh2:
Οποιος το εχει τωρα και δεν το καψει ειναι πια
συλλεκτικο
- 17 June 2006
- 49,660
βασικά εσύ έχεις.
Τί θέλεις?
αυτός είναι ο αρχικός ορίτζιναλ κατασκευαστής. (και προτεινόμενος από τον λαμπιζάτορα)
Εχει και καλύτερο μτσ.
από εκεί πήρα εγώ.
D I M __ Z
AVClub Fanatic
το δικό μου είναι ακόμα άσφαχτο ......
λες να είναι .....
http://www.youtube.com/watch?v=ygNuRpwZqRU
λες να είναι .....
http://www.youtube.com/watch?v=ygNuRpwZqRU
- 17 June 2006
- 49,660
